The present disclosure relates to an integrated circuit designing device for designing integrated circuits, an integrated circuit designing method, and a recording medium having an integrated circuit designing program recorded thereon. In particular, the present disclosure relates to an integrated circuit designing device capable of efficiently executing a wiring design for shielded clock wiring used in an integrated circuit, an integrated circuit designing method, and a recording medium having an integrated circuit designing program recorded thereon.
Clock wiring used in integrated circuits must transmit a clock signal to an entire integrated circuit, and is therefore thicker than the wiring used to connect circuit cells. However, the clock wiring carries a high frequency clock signal.
As a result of these factors, the clock wiring is a source of noise which adversely affects neighboring wiring.
In view of the adverse effects of the generated noise, when integrated circuits are designed, shield wiring is provided on both sides of the clock wiring to prevent adverse effects on the neighboring wiring.
It is well known (see Japanese Unexamined Patent Application Publication No. H10-313056, for instance) that providing shield wiring in this way allows a reduction in the radiated noise from the integrated circuit.
One way to reduce the effects of the noise from the clock wiring on neighboring wiring is to narrow the thickness of the clock wiring. This is because reducing the thickness of the clock wiring reduces the range of the noise effects.
Thus, the effects can be reduced by constructing the clock wiring from a plurality of narrow wires rather than a single thick wire.
In Japanese Unexamined Patent Application Publication No. 2001-142915, the inventor discloses an invention for integrated circuit design using a layer-type layout method. The invention takes into account constraints on metal density due to characteristics of the semi-conductor, and, when single-wire wiring is specified and a thickness of the single-wire wiring is greater than or equal to a prescribed value, divides the single-wire wiring into a plurality of wires.
Japanese Unexamined Patent Application Publication No. H6-342456 discloses another invention for integrated circuit design. To ensure that wiring can be provided automatically without problems such as shorting caused by divergence of parallel wiring, wires that are to be bunched together are combined to form wide single-wire bunch-state wiring. After the remaining wiring has been drawn, the wide bunch-state wiring is divided.
When designing integrated circuits, providing shield wiring on both sides of the clock wiring is an extremely effective method of preventing adverse effects on the neighboring wiring.
However, the wiring pattern for this type of shielded clock wiring is complex, and so substantial work is required when it becomes necessary to revise the layout of a wired circuit.
There is, however, no technology in the related art for realizing the wiring for shielded clock wiring in an efficient manner.
To reduce the effects of the noise from the clock wiring on neighboring wiring, it is preferable that the thickness of the clock wiring is reduced.
However, for every reduction in the thickness of the clock wiring, the number of clock wires has to increase, and this change requires a substantial amount of work.
One way of addressing this problem is a method by which single-wire shielded clock wiring is provided and subsequently divided.
However, when designing an integrated circuit, providing and subsequently dividing single-wire shielded clock wiring can not be realized by simply dividing wiring.
In other words, not just the clock wiring, but all the wiring used in integrated circuits is subject to spatial constraints. New wiring cannot be provided in areas where wiring already exists. Moreover, even if an area in which the new wiring is to be provided is free, if the required gap between the new wiring and neighboring wiring cannot be secured, the new wiring cannot be provided in the area.
Therefore, even when single-wire shielded clock wiring has been successfully wired within the space constraints, wiring of the shielded clock wiring after division is not always possible.
Also, in the case of clock wiring, even if wiring is achieved in the available space, it is sometimes necessary to supply a synchronous clock to a plurality of different circuit cells, and so delay times must be considered when determining the final clock wiring layout.
Thus, even if the single-wiring shielded clock wiring can be wired so that the clock is synchronously supplied to the circuit cells which require a synchronous clock, it is sometimes the case that the clock cannot be supplied to the circuit cells synchronously once the single shielded clock wiring has been divided.
Therefore, when designing integrated circuits, providing and subsequently dividing single-wire shielded clock wiring can not be realized by simply dividing wiring.
Moreover, conventional technology for dividing single-wire wiring does not provide a technique for restoring the divided wiring to an original single-wire form.
When a layout including divided wiring is to be revised, it is sometimes the case that restoring the divided wiring to the original single-wire allows revision in a single operation and thereby simplifies the revision. However, conventional technology does not provide this capability.
The present disclosure was conceived upon consideration of these problems with the object of providing a new integrated circuit design technology capable of efficiently executing designs for shielded clock wiring during integrated circuit design.